As the integration densities of dynamic random access memory devices increase, the area available for each memory cell decreases thus decreasing the area available for each memory cell capacitor. Accordingly, an increase in the integration density of a DRAM may result in a decrease in the capacitance of each memory cell capacitor increasing the soft error rate. In addition, a smaller memory cell capacitor with reduced capacitance may require a higher operating voltage thus increasing power consumption. Further increases in integration densities may thus require that memory cell capacitors occupying smaller areas of memory devices have a higher capacitance per unit area.
In general, a 64 Mb DRAM may have a memory cell area of about 1.5 .mu.m.sup.2. It may thus be difficult to obtain a sufficient capacitance using a conventional two-dimensional stacked memory cell even if the dielectric layer is formed from a material having a relatively high dielectric constant such as tantalum oxide (Ta.sub.2 O.sub.5). Three-dimensional stacked capacitor structures have thus been suggested. For example, capacitors having double stack structures, fin structures, cylindrical electrode structures, spread stack structures, and box structures have been suggested to increase the cell capacitances of memory cells.
FIGS. 1 to 3 are cross sectional views illustrating steps of a conventional method for fabricating a capacitor for an integrated circuit device. As shown in FIG. 1, a semiconductor substrate 1 is divided by the field oxide layer 3 into active and nonactive areas. A transistor including a drain region 5, a source region 7, and a gate electrode 9 is formed in the active area of the semiconductor substrate 1. An insulation layer 11 is formed on the gate electrode 9 for insulating the gate electrode 9, and a buried bit line 13 is formed in contact with the drain region 5. An interlayer dielectric layer (ILD) 15 is then formed on the entire surface of the resulting structure, and portions of the ILD 15 are selectively etched to form contact holes 17 exposing source regions 7.
As shown in FIG. 2, a polysilicon layer 19 is formed on the ILD 15 filling the contact holes 17, and a patterned photoresist layer 21 is formed on the polysilicon layer 19. The polysilicon layer 19 is etched using the patterned photoresist layer 21 as a mask forming storage electrodes 19a as shown in FIG. 3. The patterned photoresist layer 21 is then removed. A dielectric layer 23 and a plate electrode 25 are then formed on the entire surface of the storage electrodes 19a, thereby completing the capacitor structure. In particular, the plate electrode 25 can be formed from a layer of polysilicon.
According to the method discussed above, the thickness of the polysilicon layer 19 for the storage electrode can be increased to increase the memory cell capacitance. If the thickness of the polysilicon layer 19 is increased, however, the step difference between the cell array region and the peripheral circuit region of the integrated circuit device may increase, thus complicating metal wiring processes which may follow.